The present invention relates to semiconductor devices, and relates particularly, but not exclusively, to semiconductor charge storage devices such as semiconductor memories, and to substrates for manufacturing such devices.
International patent application PCT/EP02/06495 discloses a DRAM (Dynamic Random Access Memory) device comprising a matrix of memory cells, each cell being formed by a field effect transistor. By applying suitable voltage pulses between the gate and drain and between the source and drain of each transistor, an electric charge can be generated and stored in the body of the transistor, the presence or absence of the charge representing a “1” or “0” state of a binary data bit. Memory devices using SOI (Silicon On Insulator) type field effect transistors are disclosed in more detail in “SOI technology: materials to VLSI”, second edition, Kluwer, Boston 1997.
The transistors used in this type of device are PD-SOI (partially depleted silicon on insulator) transistors, which are formed in a layer of silicon formed on an insulating layer, the source, body and drain of each transistor being formed in the same layer, throughout the whole thickness of the silicon layer. The silicon layer is then covered by a dielectric film on which the gate of each transistor is formed.
To enable a charge to be stored in the body of a transistor of this type, it is necessary for the body of the transistor to have a sufficiently thick layer of silicon at its central part to provide the silicon with a non-depleted region, known as the neutral region, the charge being stored in, or in the proximity of, this latter region. As a consequence, such transistors are known as partially depleted transistors.
FD-SOI (fully depleted silicon on insulator) transistors are known, in which the silicon layer in which the source and drain regions are formed is thinner and/or the doping is less concentrated than in the case of partially depleted SOI transistors, as a result of which no neutral zone is provided. This means that it is not possible to store a charge in the body of such transistors. However, FD-SOI transistors present a number of advantages compared with partially depleted transistors, for example excellent short channel behavior and a very rapid switching frequency. These advantages result from the small thickness of the silicon layer.
A comparison of the construction of bulk and SOI transistors is shown in FIGS. 1 and 2. Referring to FIGS. 1a and 2a, an SOI transistor is formed from a substrate 10 having a substrate layer 12 of silicon, an insulating layer 14 of silicon oxide or sapphire, and a silicon layer 16. In the case of a transistor using bulk technology, as shown in FIGS. 1b and 2b, the substrate 10 comprises only the silicon substrate layer 12.
Referring to FIGS. 2a and 2b, in which parts common to both types of device are denoted by like reference numerals, integrated circuits comprising field effect transistors (of which only one is shown in each of FIGS. 2a and 2b) are formed on the substrates 10 by successive photolithographic operations in which layers are partially removed, doped or new layers are deposited. The field effect transistor shown in FIG. 2a has a source 18 and a drain 20 formed in layer 16, a body 22 being defined between the source 16 and drain 20, the source 18 and drain 20 extending through the full depth of layer 16. As will be familiar to persons skilled in the art, the source 18, drain 20 and body 22 are formed by doping of the silicon of layer 16. The body 22 is covered by a dielectric film 24 overlapping with source 18 and drain 20, and on which a gate 26 is provided. The layer 26 is removed around the source 18 and drain 20, and replaced by an insulating framework 28 of silicon oxide. When a suitable voltage is applied to the gate 26, an electrically conducting channel 30 connecting the source 18 and drain 20 forms at the surface of the body 22 at the interface with dielectric film 24.
Referring to FIG. 2b, the source 18 and drain 20 are formed in substrate layer 12 to define the body 22 between the source and the drain, and the dielectric film 24 covers the body 22 and overlaps the source 18 and drain 20.
Referring now to FIGS. 3a and 3b, FIG. 3b shows the variation of potential with thickness z (measured from the interface with dielectric film 24) of region B in the bulk transistor of FIG. 3a. The graph shown in FIG. 3b shows curves Bc, Bv and Nf, representing the potential of the valence band, the conduction band and the Fermi level respectively at the interior of body 22. Similarly, FIGS. 4a and 4b show corresponding diagrams for a PD-SOI transistor, and FIGS. 5a and 5b show corresponding diagrams for a FD-SOI transistor.
It can be seen from FIGS. 3b to 5b that the valence band Bv and conduction band Bc have a minimum value of potential at the interface of body 22 and dielectric film 24 in the case of each type or transistor. However, it can be seen from FIG. 3b that the potentials Bv and Bc vary in a first zone Zd, and tend towards a limiting value beyond which a second zone Zn, known as the neutral zone, starts. This second zone Zn extends through the total thickness of the substrate layer 12. When a suitable voltage is applied to gate 26, an electrically conducting channel 30 forms at the surface of the body 22 at the interface with dielectric film 24.
Referring now to FIG. 4b, it can be seen that the PD-SOI transistor has two depletion zones Zd1 and Zd2, adjacent dielectric film 24 and insulting layer 14 respectively, between which is located a neutral zone Zn. It will be appreciated by persons skilled in the art that the shape and extent of depletion zone Zd2 depends upon the back gate potential relative to the front gate potential. It is possible to store an electric charge in the body 22, in particular in, or in the proximity of, neutral zone Zn located between the two depletion zones Zd1 and Zd2. One possible application of such a transistor is as an individual memory cell, capable of representing two logic states depending upon the presence or absence of charge in or in the proximity of the neutral zone Zn, for forming a semiconductor memory device such as a DRAM.
Referring now to FIG. 5b, it can be seen that in the case of the FD-SOI transistor, the potential of the conduction band Bc and valence band Bv varies continually throughout the entire thickness of body 22. In other words, the body 22 has a depletion zone Zd extending throughout its entire thickness, as a result of which no neutral zone exists. It is therefore not possible to store charge in the body 22, and the transistor of this type therefore cannot be used as a memory cell. However, transistors of this type have a number of advantages, in particular excellent short channel behaviour and a very rapid switching frequency, these properties being as a result of the small thickness of layer 16.